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<pre>
 
cpldfit:  version O.76xd                            Xilinx Inc.
                                  Fitter Report
Design Name: CPx2                                Date:  1-25-2012,  6:12AM
Device Used: XCR3064XL-6-VQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
17 /64  ( 27%) 9   /192  (  5%) 20  /160  ( 12%) 6  /64  (  9%) 37 /64  ( 58%)

** Function Block Resources **

Function  Mcells    FB Inps   Pterms    IO        GCK       
Block     Used/Tot  Used/Tot  Used/Tot  Used/Tot  Used/Tot  
FB1        15/16     16/40      7/48    15/15*     1/2
FB2         2/16      4/40      2/48     2/15      0/2
FB3         0/16      0/40      0/48     0/15      0/2
FB4         0/16      0/40      0/48     0/15      0/2
           -----    -------   -------    -----
Total      17/64     20/160     9/192   17/60 

* - Resource is exhausted

** Local Control Term Resources **

        LCT0     LCT1     LCT2     LCT3     LCT4     LCT5     LCT6     LCT7
FB1                                         ce                                  
FB2                                                                             
FB3                                                                             
FB4                                                                             

Legend:
ce   - clock enable
clk  - clock
oe   - output enable
sr   - set/reset
uct1 - universal control term clock
uct2 - universal control term output enable
uct3 - universal control term preset
uct4 - universal control term reset
LCT0 - oe and/or sr can be mapped to this local control term
LCT1 - oe and/or sr can be mapped to this local control term
LCT2 - oe and/or sr can be mapped to this local control term
LCT3 - sr can be mapped to this local control term
LCT4 - ce and/or clk and/or sr can be mapped to this local control term
LCT5 - clk and/or sr can be mapped to this local control term
LCT6 - clk and/or oe can be mapped to this local control term
LCT7 - clk can be mapped to this local control term

** Global Control Resources **

GCK         UCLK        UOE         UPST        URST        
Used/Tot    Used/Tot    Used/Tot    Used/Tot    Used/Tot
1/4         0/1         0/1         0/1         0/1

GCK  - Global Clock
UCLK - Universal Control Term Clock
UOE  - Universal Control Term Output Enable
UPST - Universal Control Term Preset
URST - Universal Control Term Reset

Signal 'N_WR' mapped onto global clock net GCK0.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used     Total 
------------------------------------|-------------------------------------
Input         :   19          19    |  I/O              :    36       60
Output        :   17          17    |  GCK/I            :     1        4
Bidirectional :    0           0    |  
GCK           :    1           1    |  
                 ----        ----
        Total    37           37 

End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'CPx2.ise'.
*************************  Summary of Mapped Logic  ************************

** 17 Outputs **

Signal              Total Total Loc     Pin   Pin       Pin     Slew Reg Init
Name                Pts   Inps          No.   Type      Use     Rate State
BANK<2>             2     11    FB1_1   85    I/O       O       FAST RESET
BANK<3>             2     11    FB1_2   84    I/O       O       FAST RESET
BANK<4>             2     11    FB1_3   83    I/O       O       FAST RESET
BANK<5>             2     11    FB1_4   81    I/O       O       FAST RESET
BANK<0>             2     10    FB1_5   80    I/O       O       FAST RESET
BANK<1>             2     10    FB1_6   79    I/O       O       FAST RESET
N_IORQEGDE          0     0     FB1_7   76    I/O       O       FAST 
N_ROMCS             0     0     FB1_8   75    I/O       O       FAST 
CONMEM              0     0     FB1_10  71    I/O       O       FAST 
MAPRAM              0     0     FB1_11  69    I/O       O       FAST 
N_EEPROMCS          0     0     FB1_12  68    I/O       O       FAST 
N_SRAMCS            0     0     FB1_13  67    I/O       O       FAST 
N_SRAMEN            0     0     FB1_14  65    I/O       O       FAST 
N_SRAMOE            0     0     FB1_15  64    I/O       O       FAST 
N_SRAMWR            0     0     FB1_16  63    I/O       O       FAST 
N_EEPROMWR          1     3     FB2_1   92    I/O       O       FAST 
N_EEPROMOE          1     2     FB2_2   93    I/O       O       FAST 

** 20 Inputs **

Signal              Loc     Pin   Pin       Pin     
Name                        No.   Type      Use     
N_WR                        90    GCK/I     GCK/I            
JUMPER_EEPROM       FB2_3   94    I/O       I                
N_MREQ              FB2_4   96    I/O       I                
N_RD                FB2_5   97    I/O       I                
A<0>                FB2_6   98    I/O       I                
A<1>                FB2_7   99    I/O       I                
A<2>                FB2_8   100   I/O       I                
A<3>                FB2_10  6     I/O       I                
A<4>                FB2_11  8     I/O       I                
A<5>                FB2_12  9     I/O       I                
A<6>                FB2_13  10    I/O       I                
A<7>                FB2_14  12    I/O       I                
D<0>                FB2_15  13    I/O       I                
D<1>                FB2_16  14    I/O       I                
D<2>                FB3_2   61    I/O       I                
D<3>                FB3_3   60    I/O       I                
D<4>                FB3_4   58    I/O       I                
D<5>                FB3_5   57    I/O       I                
JUMPER_COMP_MODE    FB3_6   56    I/O       I                
N_M1                FB3_7   54    I/O       I                

Legend:
Pin No. - ~ - User Assigned
PU          - Pull Up
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               16/24
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   7/41
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
BANK<2>                       2     FB1_1   85   I/O     O     N_WR
BANK<3>                       2     FB1_2   84   I/O     O     N_WR
BANK<4>                       2     FB1_3   83   I/O     O     N_WR
BANK<5>                       2     FB1_4   81   I/O     O     N_WR
BANK<0>                       2     FB1_5   80   I/O     O     N_WR
BANK<1>                       2     FB1_6   79   I/O     O     N_WR
N_IORQEGDE                    0     FB1_7   76   I/O     O     
N_ROMCS                       0     FB1_8   75   I/O     O     
(unused)                      0     FB1_9   73   TDO/I/O       
CONMEM                        0     FB1_10  71   I/O     O     
MAPRAM                        0     FB1_11  69   I/O     O     
N_EEPROMCS                    0     FB1_12  68   I/O     O     
N_SRAMCS                      0     FB1_13  67   I/O     O     
N_SRAMEN                      0     FB1_14  65   I/O     O     
N_SRAMOE                      0     FB1_15  64   I/O     O     
N_SRAMWR                      0     FB1_16  63   I/O     O     

Signals Used by Logic in Function Block
  1: A<0>               7: A<6>              12: D<3> 
  2: A<1>               8: A<7>              13: D<4> 
  3: A<2>               9: D<0>              14: D<5> 
  4: A<3>              10: D<1>              15: JUMPER_COMP_MODE 
  5: A<4>              11: D<2>              16: N_M1 
  6: A<5>             

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
BANK<2>           XXXXXXXX..X...XX........................ 11      
BANK<3>           XXXXXXXX...X..XX........................ 11      
BANK<4>           XXXXXXXX....X.XX........................ 11      
BANK<5>           XXXXXXXX.....XXX........................ 11      
BANK<0>           XXXXXXXXX......X........................ 10      
BANK<1>           XXXXXXXX.X.....X........................ 10      
N_IORQEGDE        ........................................ 0       
N_ROMCS           ........................................ 0       
CONMEM            ........................................ 0       
MAPRAM            ........................................ 0       
N_EEPROMCS        ........................................ 0       
N_SRAMCS          ........................................ 0       
N_SRAMEN          ........................................ 0       
N_SRAMOE          ........................................ 0       
N_SRAMWR          ........................................ 0       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               4/36
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   2/46
Number of function block global clocks used/remaining:  0/2
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
N_EEPROMWR                    1     FB2_1   92   I/O     O     
N_EEPROMOE                    1     FB2_2   93   I/O     O     
(unused)                      0     FB2_3   94   I/O     I     
(unused)                      0     FB2_4   96   I/O     I     
(unused)                      0     FB2_5   97   I/O     I     
(unused)                      0     FB2_6   98   I/O     I     
(unused)                      0     FB2_7   99   I/O     I     
(unused)                      0     FB2_8   100  I/O     I     
(unused)                      0     FB2_9   4    TDI/I/O       
(unused)                      0     FB2_10  6    I/O     I     
(unused)                      0     FB2_11  8    I/O     I     
(unused)                      0     FB2_12  9    I/O     I     
(unused)                      0     FB2_13  10   I/O     I     
(unused)                      0     FB2_14  12   I/O     I     
(unused)                      0     FB2_15  13   I/O     I     
(unused)                      0     FB2_16  14   I/O     I     

Signals Used by Logic in Function Block
  1: JUMPER_EEPROM      3: N_RD               4: N_WR 
  2: N_MREQ           

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
N_EEPROMWR        XX.X.................................... 3       
N_EEPROMOE        .XX..................................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Number of function block global clocks used/remaining:  0/2
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB3_1   62   TCK/I/O       
(unused)                      0     FB3_2   61   I/O     I     
(unused)                      0     FB3_3   60   I/O     I     
(unused)                      0     FB3_4   58   I/O     I     
(unused)                      0     FB3_5   57   I/O     I     
(unused)                      0     FB3_6   56   I/O     I     
(unused)                      0     FB3_7   54   I/O     I     
(unused)                      0     FB3_8   52   I/O           
(unused)                      0     FB3_9   48   I/O           
(unused)                      0     FB3_10  47   I/O           
(unused)                      0     FB3_11  46   I/O           
(unused)                      0     FB3_12  45   I/O           
(unused)                      0     FB3_13  44   I/O           
(unused)                      0     FB3_14  42   I/O           
(unused)                      0     FB3_15  41   I/O           
(unused)                      0     FB3_16  40   I/O           
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Number of function block global clocks used/remaining:  0/2
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB4_1   15   TMS/I/O       
(unused)                      0     FB4_2   16   I/O           
(unused)                      0     FB4_3   17   I/O           
(unused)                      0     FB4_4   19   I/O           
(unused)                      0     FB4_5   20   I/O           
(unused)                      0     FB4_6   21   I/O           
(unused)                      0     FB4_7   23   I/O           
(unused)                      0     FB4_8   25   I/O           
(unused)                      0     FB4_9   29   I/O           
(unused)                      0     FB4_10  30   I/O           
(unused)                      0     FB4_11  31   I/O           
(unused)                      0     FB4_12  32   I/O           
(unused)                      0     FB4_13  33   I/O           
(unused)                      0     FB4_14  35   I/O           
(unused)                      0     FB4_15  36   I/O           
(unused)                      0     FB4_16  37   I/O           
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_BANK0: FDCPE port map (BANK(0),D(0),N_WR,'0','0',BANK_CE(0));
BANK_CE(0) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
	A(7) AND NOT A(3) AND NOT A(2));

FDCPE_BANK1: FDCPE port map (BANK(1),D(1),N_WR,'0','0',BANK_CE(1));
BANK_CE(1) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
	A(7) AND NOT A(3) AND NOT A(2));

FDCPE_BANK2: FDCPE port map (BANK(2),BANK_D(2),N_WR,'0','0',BANK_CE(2));
BANK_D(2) <= (JUMPER_COMP_MODE AND D(2));
BANK_CE(2) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
	A(7) AND NOT A(3) AND NOT A(2));

FDCPE_BANK3: FDCPE port map (BANK(3),BANK_D(3),N_WR,'0','0',BANK_CE(3));
BANK_D(3) <= (JUMPER_COMP_MODE AND D(3));
BANK_CE(3) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
	A(7) AND NOT A(3) AND NOT A(2));

FDCPE_BANK4: FDCPE port map (BANK(4),BANK_D(4),N_WR,'0','0',BANK_CE(4));
BANK_D(4) <= (JUMPER_COMP_MODE AND D(4));
BANK_CE(4) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
	A(7) AND NOT A(3) AND NOT A(2));

FDCPE_BANK5: FDCPE port map (BANK(5),BANK_D(5),N_WR,'0','0',BANK_CE(5));
BANK_D(5) <= (JUMPER_COMP_MODE AND D(5));
BANK_CE(5) <= (A(6) AND A(5) AND A(1) AND A(0) AND NOT A(4) AND N_M1 AND 
	A(7) AND NOT A(3) AND NOT A(2));


CONMEM <= '0';


MAPRAM <= '0';


N_EEPROMCS <= '0';


N_EEPROMOE <= (N_MREQ AND N_RD);


N_EEPROMWR <= (N_MREQ AND N_WR AND JUMPER_EEPROM);


N_IORQEGDE <= '1';


N_ROMCS <= '1';


N_SRAMCS <= '0';


N_SRAMEN <= '0';


N_SRAMOE <= '0';


N_SRAMWR <= '0';


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XCR3064XL-6-VQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13               XCR3064XL-6-VQ100              63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 NC                               51 VCC                           
  2 NC                               52 WPU                           
  3 VCC                              53 NC                            
  4 TDI                              54 N_M1                          
  5 NC                               55 NC                            
  6 A<3>                             56 JUMPER_COMP_MODE              
  7 NC                               57 D<5>                          
  8 A<4>                             58 D<4>                          
  9 A<5>                             59 GND                           
 10 A<6>                             60 D<3>                          
 11 PE                               61 D<2>                          
 12 A<7>                             62 TCK                           
 13 D<0>                             63 N_SRAMWR                      
 14 D<1>                             64 N_SRAMOE                      
 15 TMS                              65 N_SRAMEN                      
 16 WPU                              66 VCC                           
 17 WPU                              67 N_SRAMCS                      
 18 VCC                              68 N_EEPROMCS                    
 19 WPU                              69 MAPRAM                        
 20 WPU                              70 NC                            
 21 WPU                              71 CONMEM                        
 22 NC                               72 NC                            
 23 WPU                              73 TDO                           
 24 NC                               74 GND                           
 25 WPU                              75 N_ROMCS                       
 26 GND                              76 N_IORQEGDE                    
 27 NC                               77 NC                            
 28 NC                               78 NC                            
 29 WPU                              79 BANK<1>                       
 30 WPU                              80 BANK<0>                       
 31 WPU                              81 BANK<5>                       
 32 WPU                              82 VCC                           
 33 WPU                              83 BANK<4>                       
 34 VCC                              84 BANK<3>                       
 35 WPU                              85 BANK<2>                       
 36 WPU                              86 GND                           
 37 WPU                              87 TIE                           
 38 GND                              88 TIE                           
 39 VCC                              89 TIE                           
 40 WPU                              90 N_WR                          
 41 WPU                              91 VCC                           
 42 WPU                              92 N_EEPROMWR                    
 43 GND                              93 N_EEPROMOE                    
 44 WPU                              94 JUMPER_EEPROM                 
 45 WPU                              95 GND                           
 46 WPU                              96 N_MREQ                        
 47 WPU                              97 N_RD                          
 48 WPU                              98 A<0>                          
 49 NC                               99 A<1>                          
 50 NC                              100 A<2>                          


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xcr3064xl-6-VQ100
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : PULLUP
Set Input-Only Termination                  : FLOAT
Set Universal Control Term Optimization     : OFF
Enable Foldback NANDs                       : OFF
Reserve ISP Pins                            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Input Limit                                 : 32
Pterm Limit                                 : 28
</pre>
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